1. Field of the Invention
This invention relates to a semiconductor memory device. More particularly, it relates to a semiconductor memory device having an error detecting and correcting (hereinafter referred to as ECC) function.
2. Description of the Prior Art
In recent years, with the advance of the degree of integration of semiconductor memory devices, the malfunction of memory cells due to penetration of .alpha. particles, or soft error, has become a problem. As a countermeasure, on-chip ECC having ECC function on the same semiconductor board has been used. For such on-chip ECC, refer to "Error-Correcting Codes for Semiconductor Memory Applications: A State-of-the-Art Review" IBM J. RES. DEVELOP VOL 28, No. 2 MARCH 1984, Japanese Patent Application Laid-Open No. 143600/1981 entitled "Device for Preventing Accumulation of Errors on Data," and "Dynamic testing of memory arrays which utilise ECC logic" Electronic Engineering Mid-March, 1981.
FIG. 1 is a block diagram of a conventional on-chip ECC semiconductor memory device using the Hamming code as an error correcting code.
First, referring to FIG. 1, a conventional on-chip ECC semiconductor memory device will be described. Data bits a are inputted to an input terminal 1. The data bits a are given to a write check bit generating circuit 2 and a data bit array 31 included in a memory cell array 3. The write check bit generating circuit 2 serves to generate write check bits b from the data bits a. Write check bits b generated in the write check bit generating circuit 2 are given to a check bit array 32 included in the memory cell array 3. The data bit array 31 serves to output new data bits c from the inputted data bits a. The new bits c are given to a read check bit generating circuit 4 and to a data correcting circuit 7. The check bit array 32 serves to output new write check bits d on the basis of the write check bits b. The new write check bits d are given to a syndrome generating circuit 5 and to a data correcting circuit 7.
On the basis of the inputted data bits c, the read check bit generating circuit 4 generates read check bits e, which are then given to the syndrome generating circuit 5. The syndrome generating circuit 5 has an exclusive-OR function and outputs a syndrome f. This syndrome f is given to a syndrome decoder 6. The syndrome decoder 6 decodes the syndrome f to output syndrome decode data g, which is given to the data correcting circuit 7. The data correcting circuit 7 corrects the data bits c and write check bits d on the basis of the syndrome decode data g and outputs corrected data h and external output-purpose data i. The corrected data h outputted from the data correcting circuit 7 is given to the memory cell array 3, while the external output-purpose data i is given to an address decoder 8. The address decoder 8 serves to select, on the basis of an address signal k, external output data j to be outputted to the outside from the external output-purpose data i, the selected external output data j being outputted to an output terminal 9.
The operation of the on-chip ECC semiconductor memory device shown in FIG. 1 will now be described. At the time of writing of m.sub.0 data bits a inputted to the input terminal 1, the write check bit generating circuit 2 generates write check bits (e.g., k bits) b with respect to a plurality of data bits (e.g., m bits) including data bits a. These write check bits b and m data bits a are written to the check bit memory cell array 32 and data bit memory cell array 31. A block of said (m+k) bits is used as a unit for ECC, the error detection and correction being made for each block.
At the time of reading of data from the memory cell array 3, m data bits c and k write check bits d are simultaneously read. The read check bit generating circuit 4 generates read check bits e as new check bits from said m data bits c. The syndrome generating circuit 5 finds the exclusive-OR, bit by bit, of read check bits e and write check bits d read from the memory cell array 3. Thus, a decision is made that if all bits are "0" then there is no error or otherwise there is an error.
That all bits are "0" means that the read check bits e and write check bits d coincide with each other. The data from exclusive-OR operation described above is referred to as syndrome. This syndrome is a row of data consisting of k bits. The syndrome generating circuit 5 gives syndrome f to the syndrome decoder 6.
The aforesaid syndrome f contains positional information on error bits, and which bit in the m data bits in an error can be found by decoding said positional information by the syndrome decoder 6. In accordance with this, the data correcting circuit 7 corrects or reverses the error bits in the m data bits c and k write check bits d. Generally, it is only m.sub.0 bits in the group of m corrected data that become an external data output. In this case, m.sub.0 .ltoreq.m bits. Therefore, external output data j outputted from the address decoder 8 are selected and outputted in accordance with address information k inputted to the address decoder 8. In many cases, the address decoder 8 may serve mostly or completely as an access-purpose decoder (not shown).
The write check bit generating circuit 2 and read check bit generating circuit 4 are circuits adapted to produce check bits from the m data bits in accordance with the structure of error checking and correcting code and since the logical operation is the same for both, a common circuit may serve for the two circuits. Further, the syndrome generating circuit 5, as described above, is a circuit adapted to compute the exclusive-OR, bit by bit, of the write check bits d read from the memory cell array 3 and the read check bits e newly generated form the data bits c in the read check bit generating circuit 4. The syndrome decoder 6 is a decoder for converting the k bit syndrome f into a (m+k)-bit code for specifying error bits among the m data bits c and k write check bits d; for example, there will be obtained an output such that among the (m+k) bits, error bit positions alone are "1" and the others are "0".
The data correcting circuit 7 is a circuit for computing the exclusive-OR, bit by bit, of syndrome decode data g to be outputted from the syndrome decoder 6, data bits c to be corrected and write check bits d, whereby error bit data alone is corrected or reversed. The error-corrected (m+k)-bit data h is rewritten to a predetermined address in the memory cell array 3. Further, m.sub.0 accessed data bits among the m corrected data bits i are selected by the address decoder 8, serving as external output data j.
The semiconductor memory device having on-chip ECC constructed in the manner described above must have its ECC function tested; that is, the data bit array 31, check bit array 32 and ECC circuit system must be tested. However, the recent advance of the degree of integration of on-chip ECC function-equipped semiconductor memory devices has led to a problem that the time required for these functional tests increases.